1. Field of the Invention
The present invention generally relates to design structures for fabricating trench capacitors and, more particularly, to design structures for trench capacitor fabrication which is free of requirements for process commonality and thus applicable to decoupling functions, particularly for application specific integrated circuits (ASICs).
2. Description of the Prior Art
Use of capacitors in integrated circuits has led to the design of many different configurations of the plates and dielectric thereof in an effort to better match the electrical and mechanical characteristics to the requirements imposed by the overall integrated circuit design. In particular, compared to large arrays of small capacitors in memories, decoupling applications to prevent variations in voltage caused by current load at one part of a circuit such as an integrated circuit from propagating to another part of the circuit require capacitors of relatively large size and capacitance value in relatively small numbers, often individually in specific locations on a chip which is generally densely integrated with other types of structures.
It is recognized in semiconductor manufacture that the formation of many types of structures may be affected by local conditions at the reaction interface. For this reason, it has often been the practice for reliably forming structures in small numbers, to form additional or “dummy” structures surrounding or interspersed with the structures of interest. Formation of such additional structures beyond those required not only improves reliability of formation of the intended structures but may also provide a degree of redundancy for substitution for and structures having marginal properties. However, doing so for larger structures to meet minimum pattern density constraints consumes correspondingly more chip space.
Additionally, process cost and compatibility are unavoidable concerns in integrated circuit manufacture and often require trade-offs or impose constraints on technologies which can be utilized as well as device complexity such as collars, multiple polysilicon fill deposits for deep trench capacitors and complexity of contact formation. For example, MOS transistors are often the technology of choice for application specific integrated circuits (ASICs) but have required MOS capacitors for decoupling even though MOS capacitors exhibit significant leakage while development of large capacitances is difficult and consumes large chip space. Further, known methods of fabricating decoupling capacitors has required formation of the capacitors prior to defining the active area(s) of the chip, generally with recessed isolation or shallow trench isolation (STI) formation requiring a hard mask and is thus incompatible with the soft mask process of choice.